The present invention relates to a well structure of a semiconductor memory device.
Normally, a memory cell array of a semiconductor memory device, a DRAM, for example, is divided into a plurality of blocks or sub-cell arrays, and a plurality of memory cells are arranged in each of the sub-cell arrays.
In a conventional DRAM having a plurality of sub-cell arrays, one sense amplifier is inserted between the adjacent two sub-cell arrays. In this type of DRAM, the sense amplifier is selectively connected to the bit lines of the two adjacent sub-cell arrays. In the DRAM, there is a region which is between the two adjacent sub-cell arrays and in which a sense amplifier circuit and the related circuits are formed. Such a region will be hereinafter referred to as a sense amplifier circuit region in the description below.
FIG. 1 shows a well structure of a sense amplifier circuit region of a conventional DRAM. Referring to FIG. 1, two sub-cell arrays MCA1 and MCA2 being arranged in the bit line direction and being adjacent to each other, are formed in p-type wells PWC1 and PWC2, both provided in a p-type silicon substrate Psub. In the sense amplifier circuit region SA located between the sub-cell arrays MCA1 and MCA2, there are an n-type well NW1 and two p-type wells PW1 and PW2 sandwiching the n-type well NW1.
In the p-type wells PWC1 and PWC2 where the sub-cell arrays MCA1 and MCA2 are formed, n-type wells NWB1 and NWB2 are also formed. These n-type wells NWB1 and NWB2 serve to isolate p-type wells PWC1 and PWC2 from the p-type substrate Psub and the p-type wells PW1 and PW2 of the sense amplifier circuit region SA.
The p-type wells PWC1 and PWC2 are electrically isolated by the n-type wells NWB1 and NWB2. The reason for this well structure is that the potential applied to the p-type wells PWC1 and PWC2 (where the sub-cell arrays MCA1 and MCA2 are formed) and the potential applied to the p-type wells PW1 and PW2 of the sense amplifier circuit region SA must differ from each other. To be more specific, the former potential is normally set at a negative potential so as to improve the charge holding characteristic and reduce the memory cell junction capacitance, while the latter potential is normally set at a ground potential. For this reason, it is ordinary to provide a three-well structure in a p-type silicon substrate, as shown in FIG. 1.
FIG. 2 shows the configuration of a circuit employed in the well-structure substrate shown in FIG. 1. Referring to FIG. 2, in the sub-cell arrays MCA1 and MC2A, a pair of bit lines (BL1 and bBL1; BL2 and bBL2) and word lines WL1, WL2, WL3 and WL4 are arranged, with the bit lines and the word lines intersecting each other. Dynamic memory cells MC are arranged at the intersections of these two kinds of lines. A sense amplifier circuit SA is made up of two types of sense amplifiers: one being a flip-flop type sense amplifier that employs NMOS transistors (hereinafter referred to as an NMOS sense amplifier); and the other being a flip-flop type sense amplifier that employs PMOS transistors (hereinafter referred to as a PMOS sense amplifier). The NMOS sense amplifier NSA is formed in the p-type well PW2, while the PMOS sense amplifier PSA is formed in the n-type well NW1. A column selection gate DQG is provided in the p-type well PW2, in addition to the NMOS sense amplifier NSA. A bit line equalizer circuit EQL is arranged in the p-type well PW1. In that portion of the p-type well PW1 which is closest to the sub-cell array MCA1, a switch circuit Phit1 is provided. By this switch circuit Phit1, the paired bit lines BL1 and bLB1 of the sub-cell array MCA1 are connected or disconnected from the paired bit lines BL12 and bBL12 of the sense amplifier circuit region SA. Likewise, in that portion of the p-type well PW2 which is closest to the sub-cell array MCA2, a switch circuit Phit2 is provided. By this switch circuit Phit2, the paired bit lines BL2 and bLB2 of the sub-cell array MCA2 are connected or disconnected from the paired bit lines BL12 and bBL12 of the sense amplifier circuit region SA.
Normally, in the sense amplifier circuit region SA, the PMOS sense amplifier PSA is the only element that is made of PMOS transistors. The other structural elements, namely, the bit line equalizer circuit EQL, the switch circuits Phit1 and Phit2, the column selection gate DQG, and the NMOS sense amplifiers NSA, are all made of NMOS transistors. Therefore, no element is formed in the n-type wells NWB1, NWB2 provided for isolating the well regions of the sub-cell arrays MSA1, MSA2.
As described above, no element is formed in a plurality of n-type wells used for isolating the p-type wells of the sub-cell array regions from the other p-type wells. In view of this, it is hard to say that the areas on which the n-type wells are formed are used efficiently. The larger the number of divisions of one memory cell array is, the wider will be the area required for the well isolation. This prevents efficient use of the chip area.
The present invention has been conceived in consideration of the above circumstances, and is intended to provide a semiconductor memory device which has a simple well structure and which enables efficient use of a chip area.